Clipper  :

A primary design objective of the CLIPPER was to provide an instruction set architecture that is well suited for operating systems and compilers. In this context, "well suited" means that the architecture facilitates two somewhat divergent goals :

    - The instructions should execute rapidly, preferably one per clock cycle
    - It should be easy to write programs

The first goal pushes the designer towards a very simple instruction set, with few higher level concepts supported in the hardware. This approach is often called the "Reduced Instruction Set Computer" (RISC) philosophy. The second goal pushes the designer in quite a different directrion - towards a richer instruction set with direct support for concepts from high-level languages and operating systems. This latter approach has several names - but we going to use "Complex Instruction Set Computer" (CISC) philosophy. The CLIPPER instruction set is a balance between the RISC and CISC approaches. This balance is also a characteristic of supercomputer architectures, with contain both RISC and CISC features.

Overview  :

- 33 MHz single-phase clock
- 33 MIPS
- Separate CPU data and instruction buses
- full 32 bit internal and external architecture
- 3 stage integer execution pipeline and IEEE FPU with overlapped instruction fetch and decode op.
- on chip IEEE Flotating Point Exectuion Unit
- 9 adressing modes
- most frequently used instructions execute in one clock cycle
- 16 x 32 bit user register
- 16 x 32 bit supervisor register
- 08 x 64 bit floating point register
- 4 KByte instruction cache
- 4 KByte data cache
- 256 line 2-way set associative, 16-byte line size cache organization in each cache
- 4 GByte virtual address space per process
- 4 GByte real memory address space
- 256 vectored interrupts with 16 priority levels
- 18 predefined traps
- 128 system calls